MICRO10: Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric

This paper use a FPGA to monitor the instruction stream of the main processor, which can enforce the security and array bound check requirements

MICRO10: Memory Latency Reduction via Thread Throttling

This paper propose a gather computie scatter programing style that seperate the program into computing and memory thread, and schedule both of them to make sure that the number of memory thread would not over run the limited memory bandwidth.

MICRO10: The ZCache: Decoupling Ways and Associativity

This paper seperate the concept of way and association.It can has small number of physical way, but large number of associations. It can access the physical way within one cycle if it hits, otherwise,it will search on the side path with multiply cycle to access more associations.