Time: 13:30 - 15:35 Thursday, January 22, 2009
Location: Room 414+415
8C-1 (Time: 13:30 - 13:55)
| Title | Self-Adjusting Constrained Random Stimulus Generation Using Splitting Evenness Evaluation and XOR Constraints |
| Author | Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao (Department of Computer Science and Technology, Tsinghua University, China) |
| Keyword | stimulus generation, SAT, even distribution, splitting, XOR constraint |
| Abstract | A linear dynamic method to guide random stimulus generation by SAT solvers is presented. Firstly, we analyze different evenness evaluation methods. Secondly, we applied split simplified Min-Distance-Sum evaluation methods and XOR sampling to fulfill self-adjusting random stimulus generation. Experimental results show that our method can evaluate the evenness as well as more complex formulae for stimulus generation, and also confirm that the dynamic evaluation combining with XOR sampling can improve the power of constrained simulation. |
| Title | Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input |
| Author | Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang (Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taiwan) |
| Keyword | analog/mixed-signal testing, diagnosis, design-for-test (DfT), delta-sigma modulation, integrator leakage |
| Abstract | Integrator leakage is a dominant factor in the SNR (signal-to-noise ratio) loss of delta-sigma modulators. In this paper, we propose a Design-for-Test (DfT) technique to diagnose the integrator leakage of the single-bit first-order delta-sigma modulator. The proposed technique is a low-cost solution; it only adds two multiplexers to the modulator, utilizes a single DC voltage as the test stimulus, and estimates the integrator leakage by analyzing the digitized bit stream. Furthermore, the technique can be easily extended to higher order delta-sigma modulators. Simulation results show that accurate estimations of the integrator leakage can be achieved even at the presence of noise. |
| Title | Path Selection for Monitoring Unexpected Systematic Timing Effects |
| Author | Nicholas Callegari, Pouria Bastani, Li-C. Wang (University of California, Santa Barbara, United States), Sreejit Chakravarty, Alex Tetelbaum (LSI Corp., United States) |
| Keyword | clustering, path delay, path selection, delay test |
| Abstract | This paper presents a novel path selection methodology to select paths for monitoring unexpected systematic timing effects. The methodology consists of three components: path filtering, path encoding, and path clustering. Given a large set of critical paths, in path filtering, the goal is to filter out paths that cannot be functionally sensitized. To explore the space of unexpected timing effects, a set of features are defined to encode paths into path vectors. Each feature is a source of concern that may potentially contribute to the cause of an unexpected timing effect. Finally, a kernel-based clustering algorithm is employed to group similar path vectors into clusters from which the best representative paths are selected for post-silicon monitoring. The effectiveness of our proposed methodology is demonstrated through experiments on an industrial ASIC design. |
| Title | Design for Burn-In Test: A Technique for Burn-In Thermal Stability under Die-to-Die Parameter Variations |
| Author | Mesut Meterelliyoz, Kaushik Roy (Purdue University, United States) |
| Keyword | burn-in, leakage, thermal, stability, variations |
| Abstract | Strong temperature dependence of leakage has been a major problem during burn-in test where increased voltages and temperatures are applied to weed out defective parts. Moreover, process variations may result in different temperature profiles in different dies during burn-in. This paper proposes an adaptive design-for-burn-in technique that stabilizes the junction temperature by controlling the leakage power using sleep transistors for a wide range of ambient temperatures, process variations, thermal resistances and supply voltages. |
| Title | Test Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints |
| Author | Thomas Edison Yu, Tomokazu Yoneda (Nara Institute of Science and Technology, Japan), Krishnendu Chakrabarty (Duke University, United States), Hideo Fujiwara (Nara Institute of Science and Technology, Japan) |
| Keyword | SoC test, TAM design, test scheduling, thermal-aware test, wrapper design |
| Abstract | We present a thermal-aware test-access mechanism (TAM) design and test scheduling method for system-on-chip integrated circuits. The proposed method uses cycle-accurate power profiles for thermal simulation; it also relies on test-set partitioning, test-interleaving, and bandwidth matching. We use a computationally tractable thermal-cost model to ensure that temperature constraints are satisfied and the test application time is minimized. Simulation results for the ITC’02 SOC Test Benchmarks show that, compared to prior thermal-aware test-scheduling techniques, the proposed method leads to shorter test times under tight temperature constraints. |
博文
没有评论:
发表评论